This invention re to an improved computer interface for interconnecting intelligent computer devices. More particularly, this invention relates to extensions and enhancements of the proposed American National Standard For Information Systems (ANSI) Small Computer System Interface-2 (SCSI-2), Rev. 10, described in ANSI document number X3.131-198X which is hereby incorporated by reference herein.
The SCSI-2 standard defines an I/O bus for interconnecting computers and peripheral devices. The bus can be operated over a wide range of data rates. The SCSI-2 standard provides specifications for mechanical, electrical and functional characteristics of the bus, including definitions of the physical characteristics of the bus conductors, the electrical characteristics of the signals that the conductors carry, and the meanings of those signals (e.g., control or data).
The standard further defines protocols for communicating between devices interconnected by the bus. Communication is allowed between only two devices at any given time (although up to eight devices may be interconnected by the same bus). When two devices communicate on the bus, one acts as an "initiator" and the other acts as a "target." The initiator originates an operation (i.e., requests an I/O process to be performed) and the target performs the operation.
Transfers on the bus are typically asynchronous (although a synchronous option is defined) and follow a "handshaking" protocol involving the exchange of a "Request" signal from a target and an "Acknowledge" signal from an initiator. This exchange takes place on conductors of the bus that are specifically dedicated to the handshaking task, and is performed in connection with each individual information transfer operation on the bus.
On a second logical level, the standard defines a message protocol for managing transfers on the bus. For example, a target may send a "Disconnect" message to inform an initiator that a present connection is going to be broken, and that a later reconnect will be required to complete the current I/O process. On yet another logical level, the standard defines a command and status structure. Commands are used by an initiator to request a target to perform particular I/O operations. At the completion of a command, or if for some reason a command cannot be completed by the target, the target sends a status byte to the initiator to inform the initiator of its condition.
The specifications of the SCSI-2 standard thus combine to define an interface having multiple protocol levels. The defined interface provides computer systems with device independence within a class of devices. For example, a variety of mass storage devices (such as disk drives, tape drives, optical drives, and memory caches), printers, microprocessors, and other devices can be added to a computer system without requiring modifications to system hardware or software. In addition, special features and functions of individual devices can be handled through the use of device-dependent fields and codes in the command structure.
The SCSI-2 standard further defines that initiator and target devices are daisy-chained together using a common 50-conductor "A" cable and, optionally, a 68-conductor "B" cable. When used alone, the 50-conductor A cable permits 8-bit wide data transfers. The addition of the B cable allows wider information transfers (data only) of 16 or 32 bits.
Although the SCSI-2 interface provides a convenient and powerful means for system interconnection, it has limitations. One important limitation is that messages, commands, and status information may only be transferred a single byte at a time on a designated group of eight data lines. Thus if a message, command, or status communication is more than one byte, as some of them are in the SCSI-2 protocol, separate transfer operations must be executed for each byte of the message, command, or status communication. This limits the speed of the interface. This limitation becomes particularly restrictive as computer devices become capable of responding to increasingly complicated (and longer) commands. This limitation also tends to make the prior art SCSI-2 interface less desirable for use within I/O systems in which intelligence is distributed among several processors throughout various components of the system.
An additional cost of transferring messages, commands and status information one byte at a time is that some process in each of the initiator and target devices must be executed to complete a transfer. The more message, command and status transfers that are required to perform a particular operation, the greater the burden these processes are on the respective devices.
This burden can be borne to some degree by commercially available integrated circuit chips that are designed to serve as the boundary between a "SCSI bus" and a device connected to that bus. Such commercially-available components generally have input/output terminals designed to transmit and receive the bus signals defined by the SCSI-2 standard in accordance with the electrical specifications of that standard. These components, however, typically do not have the capability to interpret the messages, commands or status information of higher protocol levels of the SCSI-2 standard, and therefore require the attention of other circuit components having that capability. For this reason, a typical SCSI circuit chip will generate interrupts each time there is a change in the signals on the SCSI bus to alert a more intelligent component, such as a microprocessor, that a change has occurred.
Servicing the interrupts generated by such a SCSI chip is a time-consuming process. In cases where the interrupts are serviced by a microprocessor, that microprocessor may be sacrificing time that could be spent on other tasks. Thus, it can be seen that, in cases where a general purpose microprocessor of a target or initiator device (e.g., a microprocessor in the controller of a mass storage device) is used to handle the interrupts generated by a SCSI chip, the requirement in the SCSI-2 standard that messages, commands and status information be sent in single byte transfers acts to increase the burden on the microprocessor, since that microprocessor must be involved with each byte transfer. This can be particularly disadvantageous in cases where a device, such as a target mass storage device, must respond to a large number of interrupts from its SCSI circuit chip during the course of a typical I/O operation.
In view of the foregoing, it would be desirable to provide an improved interface, based in part on the proposed SCSI-2 standard, which permits the parallel transfer of multiple-byte commands, messages, and/or status information.
It would also be desirable to be able to implement the protocol of such an improved interface in a manner such that data transfers across the interface can be accomplished without requiring burdensome attention from a processor in a device involved in the transfer.